{"id":32,"date":"2022-10-04T11:04:30","date_gmt":"2022-10-04T11:04:30","guid":{"rendered":"http:\/\/gr740wp.gaisler.com.linux364.unoeuro-server.com\/?page_id=32"},"modified":"2022-12-19T14:01:53","modified_gmt":"2022-12-19T14:01:53","slug":"home","status":"publish","type":"page","link":"https:\/\/gr740.space\/","title":{"rendered":"GR740 User Day 2022"},"content":{"rendered":"\n
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Welcome to
GR740 User Day 2022<\/strong><\/h1>\n\n\n\n
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13th<\/sup> of December 2022
ERASMUS Auditorium, ESTEC<\/p>\n\n\n\n

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To facilitate collaboration and to share experience between users, the GR740 User Day has been organized, where invited speakers will present applications of, and experiences with, the GR740 microprocessor.<\/p>\n\n\n\n

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U.S. EVENT<\/strong><\/a><\/div>\n<\/div>\n\n\n\n

Previous event GR740 User Day 2019<\/a><\/p>\n\n\n\n

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The GR740 device<\/a><\/strong> is a radiation-hard system-on-chip featuring a quad-core fault-tolerant LEON4 SPARC V8 processor, eight port SpaceWire router, PCI initiator\/target interface, CAN 2.0 interfaces and 10\/100\/1000 Mbit Ethernet interfaces.<\/p>\n\n\n\n

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SPEAKERS AND PRESENTATIONS<\/h1>\n\n\n\n
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Download all presentations from the 13th and 15th of December 2022 in PDF format:<\/p>\n\n\n\n

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Andrea Bufalino<\/strong> and Ivan Cappelluti<\/strong> \u2013 IPAC: TASI Platform Computer Based on GR740
On Board Computer System Engineer, Thales Alenia Space<\/em><\/p>\n\n\n\n

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Andrea Bufalino<\/strong> has been working in Thales Alenia Space Italy since 2016 as On-Board Software Engineer. He is involved in the design and development of the new generation of on-board software based on multi core and hypervisor technology. In the past years he worked on PLATiNO project and now he is working on the multicore software execution framework that will be deployed G2SB1 and Copernicus missions.<\/p>\n\n\n\n

Ivan Cappelluti<\/strong> started to work in Thales Alenia Space in 2000 as ASIC and FPGA Designer. In the past ten years he worked as On Board Computer System Engineer for the Spacebus NEO Platform and for the Copernicus Missions. Today he is engaged on future OBC architectures definition, including New Space developments, computational power improvement and A.I. capability integration.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Enrique Garcia-Nunez<\/strong> \u2013 Next Generation Processing Module for Future Payload Controllers \u2013 GR740 Payload Controller Module
Digital Hardware Engineer, Airbus Crisa<\/em><\/p>\n\n\n\n

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Enrique Garc\u00eda received a PhD in electronics engineering in 2013, focused in digital signal processing for active sensing. He has been working in Airbus Crisa since 2015 as digital hardware engineer. Since then he has been involved in several developments such as the Thermal Control Unit of the Orion ESM, Mars2020 MEDA ICU or the SMILE ECU. Currently he is the technical manager of the GR740 Payload Controller Module.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Fabio Malatesta<\/strong><\/strong> \u2013 GR765 Development Status
Hardware Engineer, CAES Gaisler Products<\/em><\/p>\n\n\n\n

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Fabio Malatesta works as Product Marketing Engineer for Gaisler Products. He has worked in hardware IP design and verification since the early stages of his career, focusing on complex SoC architectures for FPGAs and ASICs. Fabio holds degrees in Electronics Engineering and Telecommunications from the University of Rome.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Gustav Olofsson <\/strong> \u2013 GOMX-5 – Advanced Payload Processors (APPs)
Software Engineer, CAES Gaisler Products<\/em><\/p>\n\n\n\n

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My name is Gustav Olofsson and I am a Software developer working for Cobham Gaisler. During my time at Cobham Gaisler I have developed flight software for cubesat experiments and increase the quality of flight software products sold by the company. I graduated from Lule\u00e5 university of technology with a master’s degree in space.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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James Hui<\/strong> \u2013 Simics – a Deterministic Simulation Platform for Virtual GR740
System Simulation, Product Management, Wind River<\/em><\/p>\n\n\n\n

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With two decades of experience securing industrial facilities, a license as a Scrum Master, and an educational background in both engineering and philosophy, James Hui has a proven track record of assisting industry-leading customers in their security transformation.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Jan Andersson<\/strong> 
Director of Engineering, CAES Gaisler Products<\/em><\/p>\n\n\n\n

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 GR740 Development Status <\/p>\n\n\n\n

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Summary and Major Updates to the GR740 Software Ecosystem<\/p>\n\n\n\n

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Jan serves as the Director of Engineering at Gaisler in Gothenburg, Sweden. Jan joined Gaisler in 2006. He has worked with the LEON4 SPARC processor design and the Next Generation Microprocessor (NGMP, GR740) development with ESA. He has a Master of Science Degree in Embedded Systems from the Chalmers University of Technology in Gothenburg.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Mattias Holm<\/strong> \u2013 TEMU 3 and 4: High Performance Virtual GR740 Platform
Technical Project Manager, Space, Terma GmbH<\/em><\/p>\n\n\n\n

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Dr. Mattias Holm is currently the product owner and lead architect for the Terma Emulator (TEMU) full system simulator or virtual platform framework. He got his PhD in computer science, focused on compilers in 2013, and has since then been involved with supporting ESOC emulator integrations in SVFs and operational simulators; and the design and development of the TEMU multi-core emulator. Before starting his PhD, Mattias worked with flight software development (including SWARM and Cryosat 2),and spent some time as a young graduate trainee at the ESTEC flight software section.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Michael Ryan<\/strong> \u2013 OCEODmp – a whitebox RTOS for muliticore embedded systems
Professor Emeritus, DCU and O.C.E. Technology CTO<\/em><\/p>\n\n\n\n

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Studied mathematics and theoretical physics (B.Sc.) and pure mathematics (M.Sc.), worked as a statistician for a couple of years, then lecturer in mathematics, planned to stay no more than two years in academia but met a young lady and plans changed. Switched to lecturing in computing, become involved in industrial applications of microprocessors when these first emerged, consultant to various Irish and multinational companies, served on various Irish Government committees. <\/p>\n<\/div>\n<\/div>\n\n\n\n

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Mohammed Saeed Khoory<\/strong> \u2013 Development of the Emirates Lunar Rover Camera Interface Board
Lead on-board software engineer for the Emirates Lunar Mission<\/em>, MBRSC Mohammed Bin Rashid Space Centre<\/em><\/p>\n\n\n\n

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Mohammed Saeed Khoory is the lead on-board software engineer for the Emirates Lunar Mission. A graduate of computer science, he has joined MBRSC in 2012, and previously worked on the flight software for KhalifaSat as well as the operations software for the Emirates Mars Mission. He has designed and implemented the flight software of the Rashid rover’s main on-board computer, as well as lead the development of the imaging software running on the camera interface board.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Olivier Ballereau<\/strong> \u2013 Porting the ASTRO APS Platform from GR712RC to GR740
Senior Software Engineer, Jena-Optronik GmbH<\/em><\/p>\n\n\n\n

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Graduated 1999 from the Laboratoire d’Informatique Fondamentale d’Orl\u00e9ans \/ University of Orl\u00e9ans. Works since 2001 at Jena-Optronik GmbH as a Software Engineer for various space-related projects and products. After working on ground processing facilities for EUMETSAT’s EPS\/GOME-2 and some of ESA’s Envisat instruments, started to work on Jena-Optronik’s Star Tracker products. Since 2010, the focus is predominantly on embedded software, and particularly low-level platform aspects (bootloader, hardware abstraction layer, drivers, OS integration, protocol-stack, hardware-definition and -validation).<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Pablo Ghiglino<\/strong> \u2013 Klepsydra AI ported to GR740: Enabling high performance AI for Space
Founder and CEO, Klepsydra<\/em><\/p>\n\n\n\n

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Over 10-year experience in the finance industry where he was exposed to high-speed data-processing environment results in high economic impact. Parallel to his work in finance, Pablo successfully studied a PhD at the Surrey Space Center in Aerospace Engineering in the field of \u201cHigh Precision Planetary Landing\u201d with five important publications in IEEE and AIAA. After his studies, he got involved in several navigation projects, where he seized the opportunity and created Klepsydra to respond to needs for cutting AI for onboard computers by implementing software techniques inspired by work in financial trading.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Raoul Grimoldi<\/strong> \u2013 Hi-REL On board computer for low-cost applications
Head of Electronics<\/em>, OHB-Italia<\/em><\/p>\n\n\n\n

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Raoul Grimoldi is the responsible for Electrical Design in OHB-Italia (former Carlo Gavazzi Space). In this role he has followed the design of several Data Handling Systems and Space Computer for national and European missions (SarLupe, PRISMA, Formosat-5, ENMAP, EUCLID, IXPE, Comet-I). He started as digital designer, focused on Digital Signal Processing in FPGA.  He has earned a Master\u2019s degree in Electronics from Politecnico of Milan.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Roland Weigand<\/strong> \u2013 Space goes multi-core – overview of the ESA Next Generation Microprocessor development
Microelectronics Engineer<\/em>, European Space Agency<\/em><\/p>\n\n\n\n

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Graduated 1993 in Electrical Engineering and Semiconductor Physics from Ecole Sup\u00e9rieure d’Electricit\u00e9 (“Sup\u00e9lec”) in Paris \/ France. Worked as digital ASIC designer for Infineon in Munich and Tel Aviv in various consumer electronics projects (e.g. TV frame rate converter, DSL modem) dealing with integration of embedded DRAM and DSP cores. Joined ESA (European Space Agency) in 2000 as a VLSI\/ASIC Engineer. Supporting various IC development projects, a predominant topic are standard microprocessors and SoC’s built around microprocessor cores, as well as rad-hard design methodology.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Sandi Habinc<\/strong> \u2013 Moderator & Announcements
General Manager, CAES Gaisler Products<\/em><\/p>\n\n\n\n

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Serves as the General Manager of Gaisler in Gothenburg, that provides the full ecosystem to support digital hardware design for mission critical System-on-a-Chip solutions. Throughout his 20-year tenure at Gaisler, Sandi has played a vital role in establishing and promoting industry-leading embedded computer systems for commercial and aerospace applications. Sandi was a microelectronics engineer for the European Space Agency in Noordwijk, The Netherlands, where he was the design manager for various digital and mixed-signal Application Specific ICs (ASIC) projects. He has earned a Master of Science Degree in Computer Science and Engineering from the Chalmers University of Technology.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Stefan M\u00f6dlhamer<\/strong> \u2013 Building a deterministic real-time system with GR740 and TTEthernet
Senior Digital Design Engineer, TTTech<\/em><\/p>\n\n\n\n

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After joining TTTech in 2014, a Vienna-based company providing data communications networks for safety-critical applications, Stefan M\u00f6dlhamer participated on the development of TTEthernet products for space and aerospace applications, like the rad-hard TTEthernet-controller ASIC used in the flagship projects Ariane 6. Currently he is a senior digital design engineer for space and aerospace ASIC designs.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Thierry Maudire<\/strong> \u2013 PikeOS on GR740 for Space Rider
Head of Technical Sales, SYSGO S.A.S.<\/em><\/p>\n\n\n\n

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Thierry Maudire is the Head of Technical Sales at SYSGO A.G, where he manages and coordinates a team of Solution Architects to address customers technical requirements in different industries such as Aerospace & Defence, Space, Automotive, Railway, and Industrial. Thierry Maudire has about 30 years of experience specifying and developing solutions for embedded systems. Prior to SYSGO A.G. he held different positions at Wind River Systems Inc. <\/p>\n<\/div>\n<\/div>\n\n\n\n

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Thomas D\u00f6rfler<\/strong> \u2013 Improvements of the RTEMS SMP Qualification Data Package
General Manager, embedded brains GmbH<\/em><\/p>\n\n\n\n

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Dipl.-Ing. Thomas D\u00f6rfler has studied Electrical Engineering at the Technical University in Munich.  For 15 years, he worked as freelancer, trainer and consultant in several embedded projects. In 2005 he co-founded embedded brains GmbH, where he is responsible for the adaptation and extension of RTEMS for various customer projects as well as the definition and development of project specific embedded systems.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Vicente Nicolau Gallego<\/strong> \u2013 XNG support to GR740
EU Project Manager, fentISS<\/em><\/p>\n\n\n\n

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Vicente Nicolau-Gallego (male) is the EU Project Manager at fentISS and holds a Master’s Degree in Automation and Industrial Computing from the Polytechnic University of Valencia (2008). He is responsible for some research projects, developing some other management activities at the company. Prior to his current position, he worked closely in the technical field as Validation, Verification and Quality Assurance engineer during the qualification for space of LithOS according to the ECCS standards, being the responsible of the product LithOS later on. As a researcher, he has published several papers related to real time systems and has participated (and participates) in research projects funded under European Commission Framework Programmes as project coordinator.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Vilhelm Geijer<\/strong> \u2013 GR740 Single Board Computer Reference Design
Technical Lead Engineer, Beyond Gravity Sweden<\/em><\/p>\n\n\n\n

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Vilhelm Geijer is Technical Lead Engineer for computers at Beyond Gravity Sweden. He graduated from Chalmers University of Technology in 2007 with master\u2019s degree in electrical engineering. In 2009 he joined Beyond Gravity Sweden and since then has worked with the development of On Board Computers and Data Handling Systems in various roles.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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OVERVIEW<\/h1>\n\n\n\n
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MONDAY
<\/strong>12 DECEMBER<\/p>\n\n\n\n

Social Event<\/p>\n\n\n\n

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SOCIAL EVENT<\/strong><\/a><\/div>\n<\/div>\n\n\n\n

19:00 CET<\/strong><\/p>\n\n\n\n

Van der Valk Palace Hotel Noordwijk, in Paul’s Bar<\/p>\n\n\n\n

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TUESDAY
<\/strong>13 DECEMBER<\/p>\n\n\n\n

GR740 User Day 2022
ERASMUS Auditorium, ESTEC<\/p>\n\n\n\n

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REGISTRATION
GR740 USER DAY 2022<\/strong><\/a><\/div>\n<\/div>\n\n\n\n

08:30 – 17:30 CET<\/strong><\/p>\n\n\n\n

To facilitate collaboration and to share experience between users, the GR740 User Day has been organized, where invited speakers will present applications of, and experiences with, the GR740 microprocessor.<\/p>\n<\/div>\n\n\n\n

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WEDNESDAY
<\/strong>14 DECEMBER<\/p>\n\n\n\n

RISC-V in Space Workshop
ERASMUS Auditorium, ESTEC<\/p>\n\n\n\n

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RISC-V IN SPACE WORKSHOP<\/strong><\/a><\/div>\n<\/div>\n\n\n\n

08:30 – 17:30 CET<\/strong><\/strong><\/p>\n\n\n\n

The RISC-V in Space Workshop is organized by the ESA Microelectronics Section. The objective is to stimulate the exchange between different parties in Europe, providing or developing space specific microprocessors, IP cores or software solutions based on the RISC-V Instruction Set Architecture. <\/p>\n\n\n\n

Collocated with the GR740 User Day.
Both events will be located at the Erasmus Auditorium at ESTEC. Remote access will be provided for those unable to travel.<\/p>\n<\/div>\n\n\n\n

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THURSDAY
<\/strong>15 DECEMBER<\/p>\n\n\n\n

GR740 User Day 2022
U.S. Event Webinar<\/p>\n\n\n\n

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REGISTRATION
GR740 USER DAY 2022 WEBINAR<\/strong><\/a><\/div>\n<\/div>\n\n\n\n

11am – 1pm EST <\/strong>
10am – 12pm CST<\/strong>
9am – 11am MST<\/strong>
8am – 10am PST<\/strong>
17:00 – 19:00 CET<\/strong><\/p>\n\n\n\n

The GR740 User Day – U.S. Event is an on-line webinar with live presentations from our American customers.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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SCHEDULE<\/h1>\n\n\n\n
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TUESDAY
<\/strong>13 DECEMBER<\/p>\n\n\n\n

All times in CET<\/strong><\/p>\n\n\n\n

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08:00<\/p>\n<\/div>\n\n\n\n

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08:30<\/p>\n<\/div>\n\n\n\n

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Space goes multi-core \u2013 overview of the ESA Next Generation Microprocessor development<\/mark><\/strong><\/div><\/summary>
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After three generations of single core European space microprocessors, the MA31750, TSC69x (aka ERC32), AT697 (aka LEON2), the transition to multi-core was prepared within the GINA (Giga Instruction New Architecture) study, using a quad-core LEON3, completed in 2006. The development of today’s GR740 was initiated in 2009 under the code name Next Generation Microprocessor (NGMP). An enhanced architecture was defined, upgrading to LEON4, and introducing L2 cache to address the bottlenecks created by the shared bus and memory of the GINA design. After early prototypes on FPGA and commercial technology, it was not until 2014 that a suitable ASIC platform, the C65SPACE 65 nm technology from ST Microelectronics has become available. After release of EM prototypes and evaluation boards in Q2\/2016, flight parts have been manufactured and tested, they are shipping since late 2021. QML-V space qualification has been achieved in Q2\/2022. In parallel to the ceramic package, a plastic PGBA variant has been created, targeting constellations and low-cost missions. In parallel to the chip development, numerous activities to develop and improve the software ecosystem (compiler, operating system, hypervisor, timing analysis tools etc.) have been conducted.<\/p>\n\n\n\n

We are today glad to see the GR740 used by several customers in and outside of ESA member states, for missions in various sectors, earth observation, science, navigation, exploration, communication, as main on-board computer, or in payloads and other key equipment such as star trackers.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Roland Weigand<\/p>\n<\/div>\n\n\n\n

\n

European Space Agency<\/p>\n<\/div>\n<\/div>\n\n\n\n

\n\n\n\n
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08:40<\/p>\n<\/div>\n\n\n\n

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GR740 Development Status<\/strong><\/mark><\/strong><\/div><\/summary>
\n

The development of the rad-hard GR740 quad-core LEON4FT microprocessor has now been completed and the product with the ceramic package has achieved QML-V qualification earlier this year. In parallel the development of the organic package is progressing and the evaluation and lot validation is being completed. The presentation will cover the functionality of the GR740 and development status of both package variants.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Jan Andersson<\/p>\n<\/div>\n\n\n\n

\n

CAES Gaisler Products<\/p>\n<\/div>\n<\/div>\n\n\n\n

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09:05<\/p>\n<\/div>\n\n\n\n

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IPAC: TASI Platform Computer Based on GR740<\/mark><\/strong><\/div><\/summary>
\n

TAS in Italy adopted MultiCore Processor in their On Board Computer since the first announced development of ESA NGMP in 2011 up to the release of first prototype of Quad-Core Leon4FT GR740 SoC in 2015. In this 11 years the IPAC, Integrated Processor and AOCS Controller, OBC family has been developed, covering a wide range of space applications. The development covered both Hardware and Software aspects, covering several critical aspects induced by the use of such complex architecture. This presentation addresses the experience matured in the last decade and the future perspectives from user\u2019s point of view.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Ivan Cappelluti<\/p>\n<\/div>\n\n\n\n

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Thales Alenia Space<\/p>\n<\/div>\n<\/div>\n\n\n\n

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09:30<\/p>\n<\/div>\n\n\n\n

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GR740 Single Board Computer Reference Design<\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

The \u201cReference Design and Basic Software for a Single Board Computer based on GR740\u201d is a technology development activity funded by ESA, with the title reflecting the main objective of the development in the activity. The Reference Design will be available for European space users. The work will also result in an Elegant Breadboard and Basic Software to be verified on a functional and performance level, as well as a qualification test plan for future space qualification.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Vilhelm Geijer<\/p>\n<\/div>\n\n\n\n

\n

Beyond Gravity<\/p>\n<\/div>\n<\/div>\n\n\n\n

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09:55<\/p>\n<\/div>\n\n\n\n

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Porting the ASTRO APS Platform from GR712RC to GR740<\/mark><\/strong><\/div><\/summary>
\n

Jena-Optronik, based in Thuringia, Germany, is a worldwide leader in the development and manufacturing of opto-electronic sensors for the Attitude and Orbit Control Systems (AOCS) of satellites and spacecraft. Jena-Optronik\u2019s current generation of star sensors as well as LiDAR sensors utilize GR712RC, a dual-core LEON3FT SPARC V8 microprocessor.
Jena-Optronik will use flight grade GR740 quad-core LEON4FT SPARC V8 Microprocessor devices for its next-generation sensor products. The GR740 microprocessor was chosen for its software reuse, lower power, and increased processing power. The standard interfaces, scalable performance and ease of design enable the addition of even more capability to future missions while maintaining the same basic infrastructure for other designs\/products.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Olivier Ballereau<\/p>\n<\/div>\n\n\n\n

\n

Jena Optronik<\/p>\n<\/div>\n<\/div>\n\n\n\n

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10:20<\/p>\n<\/div>\n\n\n\n

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Coffee morning<\/strong><\/p>\n<\/div>\n\n\n\n

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10:50<\/p>\n<\/div>\n\n\n\n

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Development of the Emirates Lunar Rover Camera Interface Board<\/mark><\/strong><\/div><\/summary>
\n

The Emirates Lunar Rover (Rashid) is MBRSC’s first lunar and rover mission. The rover utilizes a GR740-based single board computer from AAC ClydeSpace, named the Camera Interface Board, to interface with the rover’s three SpaceWire cameras, as well as a thermal camera. The team first intended to use an ARM Cortex-based board for this purpose, but has successfully moved to a LEON4-FT based solution. The imaging software (ISW), based on GR-Linux, runs on the CIB, and performs image capture and processing tasks, storing them on a mass memory board before downloading them to the ground. During the transition from ARM to LEON4-FT, some difficulties were faced and overcome or worked around, such as performance differences and debugging difficulties.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Mohammed Saeed Khoory<\/p>\n<\/div>\n\n\n\n

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MBRSC<\/p>\n<\/div>\n<\/div>\n\n\n\n

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11:10<\/p>\n<\/div>\n\n\n\n

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Next Generation Processing Module for Future Payload Controllers \u2013 GR740 Payload Controller Module<\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Airbus Crisa (Tres Cantos \u2013 Spain) is developing the next generation processing module which will be the baseline for future Payload Controllers: the GR740 Payload Controller Module (GR740 PCM). It is based on the high performant multi-core GR740 SoC and the RTG4 reprogrammable FPGA which allow to provide a flexible HW architecture. Furthermore, the GR740 PCM is fully compliant with the ESA\u2019s ADHA standard as a System Slot and Shelf Controller, maximizing the modularity and scalability of the product. The current development will result in an Engineering Model (EM) with a TRL6 maturity level.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Enrique Garc\u00eda N\u00fa\u00f1ez<\/p>\n<\/div>\n\n\n\n

\n

Airbus CRISA<\/p>\n<\/div>\n<\/div>\n\n\n\n

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11:35<\/p>\n<\/div>\n\n\n\n

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Hi-REL On Board Computer for Low-Cost Applications<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

The design of low-cost on-board computer is not simple task if its reliability is one of the most important design goals. To keep the overall cost at low level, the classical approach based on usage of class 1 or class 2 components and redundant architecture cannot be adopted. Most of low-cost on-board computers are available from CUBESAT market where the overall quality and reliability are not a major concern. These equipments are typically designed by using commercial components which radiation behaviour is often not known or is only partially known because of the limited tests performed. In some cases, when data are not available and manufacturer cannot sustain a radiation test campaign cost, components selection criteria is done for \u201csimilarity\u201d. These approaches are very risky when also quality and reliability of the product are important features of the equipment.<\/p>\n\n\n\n

In recent years a certain number of manufacturers which provides class 1 and class 2 space qualified components are making available to space market a set of low-cost, high-reliability components that are classified as \u201cspace plastic\u201d or \u201ccommercial space\u201d.<\/p>\n\n\n\n

In the framework of preparatory activities for COMET-I project, OHB-I has been requested to design a high-reliability, low-cost on-board computer (OBC) for Probe-B2 spacecraft. OBC design adopts only radiation tolerant components belonging to \u201cspace plastic\u201d category; if requested part\/function is not available within the above-mentioned category, radiation tolerant class 3 parts have been used. No commercial parts were used.<\/p>\n\n\n\n

To comply with low mass\/volume requirement, OBC design exploits complex SoC and large FPGA to integrate all requested data handling functionalities within a small volume. The design has been developed around two radiation tolerant key components: the GR740 SoC in its organic plastic version and RTG4 FPGA in Sub-QML version. The GR740 is the processing core of the OBC, while the FPGA perform system supervising and data exchange tasks.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Raoul Grimoldi<\/p>\n<\/div>\n\n\n\n

\n

OHB Italy<\/p>\n<\/div>\n<\/div>\n\n\n\n

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\n

12:00<\/p>\n<\/div>\n\n\n\n

\n
\n
Building a deterministic real-time system with GR740 and TTEthernet<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Integration of the SW applications running on the RTOS is a complex part of the development process, especially in safety-critical systems. Application scheduling in order to optimize the usage of available system resources and verification of the system behavior interacting with external subsystems are just two examples of common topics the SW designers deal with. TTEthernet as underlying network technology for real-time and highly latency-controlled data transmission allows tight synchronization of the applications running on the CPU with the global network time. Thereby, the SW applications can rely on precise delivery of required data to be processed. In our presentation we explain architecture of such deterministic system implemented using GR740 and its usage in the safety-critical systems.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Stefan M\u00f6dlhamer<\/p>\n<\/div>\n\n\n\n

\n

TTTech<\/p>\n<\/div>\n<\/div>\n\n\n\n

\n\n\n\n
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12:25<\/p>\n<\/div>\n\n\n\n

\n
\n
GOMX-5 – Advanced Payload Processors (APPs)<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

The Advanced Payload Processors (APPs) was developed targeting in-orbit demonstration (IOD) in the GOMX-5 mission. GOMX-5 is a flight demonstration for next generation cubesat missions, which will demand advanced attitude control, large processing capabilities, and high throughput data exchange between space and ground segments. APPs was jointly conceived by Gaisler in Sweden, GMV and CBK in Poland, and UFSC in Brazil, in order to demonstrate multiple processing technologies developed within ESA activities. APPs is a 1U size payload with five stacked boards supported by a mechanical structure and interconnecting interfaces, eventually to be integrated as one of the payload modules in the 12U GOMX-5 satellite developed by Gomspace, Denmark. The APPs payload consists of one GNSS RF front-end and a DPU from GMV\/CBK, one BRAVE board from UFSC based on NanoXplore’s NG-Large FPGA, one multi-processor GR716 board from Gaisler, supervised by the fault-tolerant GR716 microcontroller, and one GR740 board, based on the fault-tolerant GR740 processor, acting as a controller and main S\/C interface for the entire APPs cube. The boards will be used for various experiments related to features such as GNSSW receiver, radiation detection, higher-performance processing and FPGA reconfiguration.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Gustav Olofsson<\/p>\n<\/div>\n\n\n\n

\n

CAES Gaisler Products<\/p>\n<\/div>\n<\/div>\n\n\n\n

\n\n\n\n
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12:50<\/p>\n<\/div>\n\n\n\n

\n

Lunch<\/strong><\/p>\n<\/div>\n\n\n\n

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<\/div>\n<\/div>\n\n\n\n
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13:50<\/p>\n<\/div>\n\n\n\n

\n
\n
Simics – a Deterministic Simulation Platform for Virtual GR740<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Wind River\u00ae Simics\u00ae is a full-system simulator used by software developers to simulate the hardware of complex electronic systems. Simics has been adapted to specifically simulate the virtual GR740 hardware. Simics allows on-demand and easy access to any target system, more efficient collaboration between developers, and more efficient and stable automation. With Simics you can adopt new development techniques that are simply not possible with physical hardware, enabling you to deliver better software faster.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

James Hui<\/p>\n<\/div>\n\n\n\n

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Wind River<\/p>\n<\/div>\n<\/div>\n\n\n\n

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14:10<\/p>\n<\/div>\n\n\n\n

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Summary and Major Updates to the GR740 Software Ecosystem<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

As the GR740 component was introduced the software ecosystem provided by CAES Gaisler was extended with support for GR740 and the necessary multi-core extensions was a primary focus at that time. The support is constantly updated as a natural response to the software universe evolution and new trends in software development, even though the main focus is around providing long term stable software packages often demanded by the space market. A brief summary of the current GR740 software ecosystem will be presented, together with major updates done by CAES Gaisler since last GR740 user-day in 2019.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Jan Andersson<\/p>\n<\/div>\n\n\n\n

\n

CAES Gaisler Products<\/p>\n<\/div>\n<\/div>\n\n\n\n

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14:30<\/p>\n<\/div>\n\n\n\n

\n
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TEMU 3 and 4: High Performance Virtual GR740 Platform<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

This presentation introduces TEMU 3 and TEMU 4.full system simulators and virtual platforms. TEMU is a full system simulation framework capable of simulating a complete board, including bus models such as Ethernet, SpaceWire and more. TEMU is focused on performance, trading of cycle accuracy for higher instruction throughput and thus faster edit-compile-debug cycles, and faster CI\/CD pipeline execution for the embedded software developer.<\/p>\n\n\n\n

TEMU 3 is the evolution of TEMU 2. While TEMU 2 has been able to simulate a dual core GR712RC in real-time, TEMU 3 ups the game with the introduction of two major performance optimisations:
Firstly, the interpreter engine has been moved from threaded fetch-decode-dispatch model to a threaded pre-decode-dispatch model. This optimisation alone yields around 50% performance gains.
Secondly a binary translation engine is introduced, resulting in another 100% speedup. The optimisations together make it possible to simulate a single GR740 core in real-time.<\/p>\n\n\n\n

TEMU 4 is currently in development and is expecting to add parallelisation of multi-core processor emulation, making it possible for a fully emulated virtual platform to simulate the GR740 quad core processor in real-time.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Mattias Holm<\/p>\n<\/div>\n\n\n\n

\n

Terma GmbH<\/p>\n<\/div>\n<\/div>\n\n\n\n

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\n

14:50<\/p>\n<\/div>\n\n\n\n

\n
\n
Improvements of the RTEMS SMP Qualification Data Package<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

In 2018-2021 the first RTEMS SMP qualification data package was developed by an ESA-funded project. It was focused on the Gaisler GR740 and the GR712 processors with a very basic functional profile and minimal interfaces. Two innovations were associated with this project:<\/p>\n\n\n\n

1. For the first time, a ECSS-qualified Open Source multicore real time operating system was made available (for Criticality Category B without ISVV)<\/p>\n\n\n\n

2. For the first time a thoroughly automated testing approach was implemented to manage the vast code complexity of RTEMS. Based on the requirements documents, tests are automatically generated and the test results collected to generate the qualification documents. This permits a maximum dynamic adaptation to recent updates.<\/p>\n\n\n\n

Meanwhile, driven by user demand, various improvements and extensions are planned or in progress. Those include:<\/p>\n\n\n\n

* UT700, GR716, GR765, NOEL-V support<\/p>\n\n\n\n

* Full code coverage for uniprocessor configuration<\/p>\n\n\n\n

* Update to latest RTEMS mainline and GCC bug fixing<\/p>\n\n\n\n

* Improved document handling and generation<\/p>\n\n\n\n

This allows extension of the qualification scope to further CPU architectures, RTEMS profiles or software packages, either by joint ESA\/ESTEC sponsored activities or based on specific user requirements.<\/p>\n\n\n\n

An important aspect when working with qualified software is code maintenance. Regarding RTEMS, this means cooperation with the RTEMS Open Source community. It is way more than just a place to download software: A big benefit for the life cycle of RTEMS is that the RTEMS Open Source community is strict in keeping the code basis maintainable and in a proper state. Therefore early planning is advisable when improvements, extensions or functional changes are to be committed to the Open Source code basis.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Thomas D\u00f6rfler<\/p>\n<\/div>\n\n\n\n

\n

Embedded Brains<\/p>\n<\/div>\n<\/div>\n\n\n\n

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15:10<\/p>\n<\/div>\n\n\n\n

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PikeOS on GR740 for Space Rider<\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

SYSGO will present how his safe and secure RTOS\/Hypervisor will be qualified on GR740 for the Onboard Computer of Space Rider ESA program.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Thierry Maudire<\/p>\n<\/div>\n\n\n\n

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SYSGO<\/p>\n<\/div>\n<\/div>\n\n\n\n

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15:30<\/p>\n<\/div>\n\n\n\n

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Coffee afternoon<\/strong><\/strong><\/p>\n<\/div>\n\n\n\n

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16:00<\/p>\n<\/div>\n\n\n\n

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XNG support to GR740<\/strong><\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

An update of the XtratuM Hypervisor support to the GR740 board.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Vicente Nicolau Gallego<\/p>\n<\/div>\n\n\n\n

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fentISS<\/p>\n<\/div>\n<\/div>\n\n\n\n

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16:20<\/p>\n<\/div>\n\n\n\n

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Klepsydra AI ported to GR740: Enabling high performance AI for Space<\/strong><\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Klepsydra software can execute Artificial Intelligence (AI) on onboard computers with limited computational capability. Klepsydra AI enables these computers consume up to 50% less energy and process up to 4 times more data than market leaders. The current commercial version of Klepsydra AI has been successfully validated in an ESA activity called KATESU, aimed at running Klepsydra AI on a Space qualified computer, with outstanding performance results.<\/p>\n\n\n\n

After the success of this project, Klepsydra has submitted a proposal to the Swiss Space Office for the adoption of Klepsydra AI to the GR740 processor running on RTMES5 operating system.<\/p>\n\n\n\n

This project is intended to be a GSTP element II and with a duration of 12 months. The goal of this development is to bring the developed technology from TRL4 to TRL7 and to carry out a performance validation on space qualified hardware.<\/p>\n\n\n\n

Since Klepsydra AI currently only support Linux operating system and ARM and x86 processor family, the adoption effort will involve substantial changes to the software to support the LEON4 architecture of GR740. Therefore, an in-depth study was carried out to produce a detailed design and implementation plan. This presentation describes in technical terms the planned project, timeline, and roadmap.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Pablo Ghiglino<\/p>\n<\/div>\n\n\n\n

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Klepsydra<\/p>\n<\/div>\n<\/div>\n\n\n\n

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16:40<\/p>\n<\/div>\n\n\n\n

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OCEOS \u2013 A new RTOS for Multicore SOCs<\/strong><\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

A RTOS designed for up to 255 CPUs, deterministic symmetric operation, fault anticipation, detection, isolation and recovery, whitebox rather than blackbox, one stack per CPU, unbounded priority inversion excluded by the design.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Michael Ryan<\/p>\n<\/div>\n\n\n\n

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OCE Technology<\/p>\n<\/div>\n<\/div>\n\n\n\n

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17:00<\/p>\n<\/div>\n\n\n\n

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GR765 Development Status<\/strong><\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Based on feedback from current GR740 users, Cobham Gaisler develops the successor, under the product name \u201cGR765\u201d. The GR765 architecture includes several improvements over the GR740. The LEON4FT has been replaced with the LEON5FT high-performance processor, increasing computational performance while at the same time providing a low-threshold upgrade path for current GR740 users that require more computational performance or that would benefit from the added on-chip functionality of the new architecture.<\/p>\n\n\n\n

The driver for the GR765 was to provide a next step for current LEON-SPARC GR740 users. At the same time, the RISC-V instruction set architecture has generated significant interest within essentially all industries, including space. To rapidly introduce RISC-V in the space domain, going beyond use of COTS or FPGA implementations, the GR765 architecture was extended with an additional mode where the eight active processor cores can either be NOEL-V RISC-V RV64GCHB processors or LEON5FT SPARC V8e processors.<\/p>\n\n\n\n

The GR765 will be implemented on STMicroelectronics 28nm FDSOI technology using libraries developed by STM for use in space applications. Improvements in processor microarchitecture, bandwidth of the system-on-chip design, and operating frequency are expected to improve the computational capacity 10x \u2013 16x compared to the GR740. In addition, the GR765 will provide significant reductions in power consumption compared to earlier generation SoCs.<\/p>\n\n\n\n

Beyond this boost on processing performance, the memory bandwidth will also be significantly increased by the use of DDR2\/3 SDRAM, the peripherals will be complemented by SerDes supporting among others the SpaceFibre standard, TTEthernet, TSN and several other enhancements.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

\n

Fabio Malatesta<\/p>\n<\/div>\n\n\n\n

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CAES Gaisler Products<\/p>\n<\/div>\n<\/div>\n\n\n\n

\n\n\n\n
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17:25<\/p>\n<\/div>\n\n\n\n

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Announcements<\/strong><\/strong><\/strong><\/mark><\/strong><\/strong><\/strong><\/strong><\/strong><\/mark><\/strong><\/div><\/summary>
\n

Announcements of new products based on, and development tools for, the GR740 processor, as well as completely new products being released before the end of the year.<\/p>\n<\/div><\/details>\n<\/div>\n<\/div>\n\n\n\n

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Sandi Habinc<\/p>\n<\/div>\n\n\n\n

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CAES Gaisler Products<\/p>\n<\/div>\n<\/div>\n\n\n\n

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17:30<\/p>\n<\/div>\n\n\n\n

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The End<\/strong><\/p>\n<\/div>\n\n\n\n

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SOCIAL EVENT<\/h1>\n\n\n\n
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You are most welcome to join us for a drink, at the opening ceremony, on December 12, 19:00 CET Van der Valk Palace Hotel Noordwijk, in Paul’s Bar.

We are looking forward to meeting You!

Sandi Habinc
General Manager, Cobham Gaisler AB<\/p>\n\n\n\n

<\/div>\n<\/div>\n<\/div>\n<\/div><\/div>\n\n\n\n
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Social event address and contact<\/h2>\n\n\n\n

December 12, 19:00 CET<\/p>\n\n\n\n

Van der Valk Palace Hotel Noordwijk, in Paul’s Bar.
Pick\u00e9plein 8, 2202 CL Noordwijk<\/p>\n\n\n\n

+31(0)713653000<\/p>\n<\/div>\n\n\n\n

\n
\"\"<\/figure>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

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