The development of the rad-hard GR740 quad-core LEON4FT microprocessor has now been completed and the product with the ceramic package has achieved QML-V qualification earlier this year. In parallel the development of the organic package is progressing and the evaluation and lot validation is being completed. The presentation will cover the functionality of the GR740 and development status of both package variants.

TAS in Italy adopted MultiCore Processor in their On Board Computer since the first announced development of ESA NGMP in 2011 up to the release of first prototype of Quad-Core Leon4FT GR740 SoC in 2015. In this 11 years the IPAC, Integrated Processor and AOCS Controller, OBC family has been developed, covering a wide range of space applications. The development covered both Hardware and Software aspects, covering several critical aspects induced by the use of such complex architecture. This presentation addresses the experience matured in the last decade and the future perspectives from user’s point of view.

The “Reference Design and Basic Software for a Single Board Computer based on GR740” is a technology development activity funded by ESA, with the title reflecting the main objective of the development in the activity. The Reference Design will be available for European space users. The work will also result in an Elegant Breadboard and Basic Software to be verified on a functional and performance level, as well as a qualification test plan for future space qualification.

Jena-Optronik, based in Thuringia, Germany, is a worldwide leader in the development and manufacturing of opto-electronic sensors for the Attitude and Orbit Control Systems (AOCS) of satellites and spacecraft. Jena-Optronik’s current generation of star sensors as well as LiDAR sensors utilize GR712RC, a dual-core LEON3FT SPARC V8 microprocessor.
Jena-Optronik will use flight grade GR740 quad-core LEON4FT SPARC V8 Microprocessor devices for its next-generation sensor products. The GR740 microprocessor was chosen for its software reuse, lower power, and increased processing power. The standard interfaces, scalable performance and ease of design enable the addition of even more capability to future missions while maintaining the same basic infrastructure for other designs/products.

The Emirates Lunar Rover (Rashid) is MBRSC’s first lunar and rover mission. The rover utilizes a GR740-based single board computer from AAC ClydeSpace, named the Camera Interface Board, to interface with the rover’s three SpaceWire cameras, as well as a thermal camera. The team first intended to use an ARM Cortex-based board for this purpose, but has successfully moved to a LEON4-FT based solution. The imaging software (ISW), based on GR-Linux, runs on the CIB, and performs image capture and processing tasks, storing them on a mass memory board before downloading them to the ground. During the transition from ARM to LEON4-FT, some difficulties were faced and overcome or worked around, such as performance differences and debugging difficulties.

Airbus Crisa (Tres Cantos – Spain) is developing the next generation processing module which will be the baseline for future Payload Controllers: the GR740 Payload Controller Module (GR740 PCM). It is based on the high performant multi-core GR740 SoC and the RTG4 reprogrammable FPGA which allow to provide a flexible HW architecture. Furthermore, the GR740 PCM is fully compliant with the ESA’s ADHA standard as a System Slot and Shelf Controller, maximizing the modularity and scalability of the product. The current development will result in an Engineering Model (EM) with a TRL6 maturity level.

The design of low-cost on-board computer is not simple task if its reliability is one of the most important design goals. To keep the overall cost at low level, the classical approach based on usage of class 1 or class 2 components and redundant architecture cannot be adopted. Most of low-cost on-board computers are available from CUBESAT market where the overall quality and reliability are not a major concern. These equipments are typically designed by using commercial components which radiation behaviour is often not known or is only partially known because of the limited tests performed. In some cases, when data are not available and manufacturer cannot sustain a radiation test campaign cost, components selection criteria is done for “similarity”. These approaches are very risky when also quality and reliability of the product are important features of the equipment.

In recent years a certain number of manufacturers which provides class 1 and class 2 space qualified components are making available to space market a set of low-cost, high-reliability components that are classified as “space plastic” or “commercial space”.

In the framework of preparatory activities for COMET-I project, OHB-I has been requested to design a high-reliability, low-cost on-board computer (OBC) for Probe-B2 spacecraft. OBC design adopts only radiation tolerant components belonging to “space plastic” category; if requested part/function is not available within the above-mentioned category, radiation tolerant class 3 parts have been used. No commercial parts were used.

To comply with low mass/volume requirement, OBC design exploits complex SoC and large FPGA to integrate all requested data handling functionalities within a small volume. The design has been developed around two radiation tolerant key components: the GR740 SoC in its organic plastic version and RTG4 FPGA in Sub-QML version. The GR740 is the processing core of the OBC, while the FPGA perform system supervising and data exchange tasks.

Integration of the SW applications running on the RTOS is a complex part of the development process, especially in safety-critical systems. Application scheduling in order to optimize the usage of available system resources and verification of the system behavior interacting with external subsystems are just two examples of common topics the SW designers deal with. TTEthernet as underlying network technology for real-time and highly latency-controlled data transmission allows tight synchronization of the applications running on the CPU with the global network time. Thereby, the SW applications can rely on precise delivery of required data to be processed. In our presentation we explain architecture of such deterministic system implemented using GR740 and its usage in the safety-critical systems.

The Advanced Payload Processors (APPs) was developed targeting in-orbit demonstration (IOD) in the GOMX-5 mission. GOMX-5 is a flight demonstration for next generation cubesat missions, which will demand advanced attitude control, large processing capabilities, and high throughput data exchange between space and ground segments. APPs was jointly conceived by Gaisler in Sweden, GMV and CBK in Poland, and UFSC in Brazil, in order to demonstrate multiple processing technologies developed within ESA activities. APPs is a 1U size payload with five stacked boards supported by a mechanical structure and interconnecting interfaces, eventually to be integrated as one of the payload modules in the 12U GOMX-5 satellite developed by Gomspace, Denmark. The APPs payload consists of one GNSS RF front-end and a DPU from GMV/CBK, one BRAVE board from UFSC based on NanoXplore’s NG-Large FPGA, one multi-processor GR716 board from Gaisler, supervised by the fault-tolerant GR716 microcontroller, and one GR740 board, based on the fault-tolerant GR740 processor, acting as a controller and main S/C interface for the entire APPs cube. The boards will be used for various experiments related to features such as GNSSW receiver, radiation detection, higher-performance processing and FPGA reconfiguration.

Wind River® Simics® is a full-system simulator used by software developers to simulate the hardware of complex electronic systems. Simics has been adapted to specifically simulate the virtual GR740 hardware. Simics allows on-demand and easy access to any target system, more efficient collaboration between developers, and more efficient and stable automation. With Simics you can adopt new development techniques that are simply not possible with physical hardware, enabling you to deliver better software faster.

As the GR740 component was introduced the software ecosystem provided by CAES Gaisler was extended with support for GR740 and the necessary multi-core extensions was a primary focus at that time. The support is constantly updated as a natural response to the software universe evolution and new trends in software development, even though the main focus is around providing long term stable software packages often demanded by the space market. A brief summary of the current GR740 software ecosystem will be presented, together with major updates done by CAES Gaisler since last GR740 user-day in 2019.

This presentation introduces TEMU 3 and TEMU 4.full system simulators and virtual platforms. TEMU is a full system simulation framework capable of simulating a complete board, including bus models such as Ethernet, SpaceWire and more. TEMU is focused on performance, trading of cycle accuracy for higher instruction throughput and thus faster edit-compile-debug cycles, and faster CI/CD pipeline execution for the embedded software developer.

TEMU 3 is the evolution of TEMU 2. While TEMU 2 has been able to simulate a dual core GR712RC in real-time, TEMU 3 ups the game with the introduction of two major performance optimisations:
Firstly, the interpreter engine has been moved from threaded fetch-decode-dispatch model to a threaded pre-decode-dispatch model. This optimisation alone yields around 50% performance gains.
Secondly a binary translation engine is introduced, resulting in another 100% speedup. The optimisations together make it possible to simulate a single GR740 core in real-time.

TEMU 4 is currently in development and is expecting to add parallelisation of multi-core processor emulation, making it possible for a fully emulated virtual platform to simulate the GR740 quad core processor in real-time.

In 2018-2021 the first RTEMS SMP qualification data package was developed by an ESA-funded project. It was focused on the Gaisler GR740 and the GR712 processors with a very basic functional profile and minimal interfaces. Two innovations were associated with this project:

1. For the first time, a ECSS-qualified Open Source multicore real time operating system was made available (for Criticality Category B without ISVV)

2. For the first time a thoroughly automated testing approach was implemented to manage the vast code complexity of RTEMS. Based on the requirements documents, tests are automatically generated and the test results collected to generate the qualification documents. This permits a maximum dynamic adaptation to recent updates.

Meanwhile, driven by user demand, various improvements and extensions are planned or in progress. Those include:

* UT700, GR716, GR765, NOEL-V support

* Full code coverage for uniprocessor configuration

* Update to latest RTEMS mainline and GCC bug fixing

* Improved document handling and generation

This allows extension of the qualification scope to further CPU architectures, RTEMS profiles or software packages, either by joint ESA/ESTEC sponsored activities or based on specific user requirements.

An important aspect when working with qualified software is code maintenance. Regarding RTEMS, this means cooperation with the RTEMS Open Source community. It is way more than just a place to download software: A big benefit for the life cycle of RTEMS is that the RTEMS Open Source community is strict in keeping the code basis maintainable and in a proper state. Therefore early planning is advisable when improvements, extensions or functional changes are to be committed to the Open Source code basis.

SYSGO will present how his safe and secure RTOS/Hypervisor will be qualified on GR740 for the Onboard Computer of Space Rider ESA program.

An update of the XtratuM Hypervisor support to the GR740 board.

Klepsydra software can execute Artificial Intelligence (AI) on onboard computers with limited computational capability. Klepsydra AI enables these computers consume up to 50% less energy and process up to 4 times more data than market leaders. The current commercial version of Klepsydra AI has been successfully validated in an ESA activity called KATESU, aimed at running Klepsydra AI on a Space qualified computer, with outstanding performance results.

After the success of this project, Klepsydra has submitted a proposal to the Swiss Space Office for the adoption of Klepsydra AI to the GR740 processor running on RTMES5 operating system.

This project is intended to be a GSTP element II and with a duration of 12 months. The goal of this development is to bring the developed technology from TRL4 to TRL7 and to carry out a performance validation on space qualified hardware.

Since Klepsydra AI currently only support Linux operating system and ARM and x86 processor family, the adoption effort will involve substantial changes to the software to support the LEON4 architecture of GR740. Therefore, an in-depth study was carried out to produce a detailed design and implementation plan. This presentation describes in technical terms the planned project, timeline, and roadmap.

A RTOS designed for up to 255 CPUs, deterministic symmetric operation, fault anticipation, detection, isolation and recovery, whitebox rather than blackbox, one stack per CPU, unbounded priority inversion excluded by the design.

Based on feedback from current GR740 users, Cobham Gaisler develops the successor, under the product name “GR765”. The GR765 architecture includes several improvements over the GR740. The LEON4FT has been replaced with the LEON5FT high-performance processor, increasing computational performance while at the same time providing a low-threshold upgrade path for current GR740 users that require more computational performance or that would benefit from the added on-chip functionality of the new architecture.

The driver for the GR765 was to provide a next step for current LEON-SPARC GR740 users. At the same time, the RISC-V instruction set architecture has generated significant interest within essentially all industries, including space. To rapidly introduce RISC-V in the space domain, going beyond use of COTS or FPGA implementations, the GR765 architecture was extended with an additional mode where the eight active processor cores can either be NOEL-V RISC-V RV64GCHB processors or LEON5FT SPARC V8e processors.

The GR765 will be implemented on STMicroelectronics 28nm FDSOI technology using libraries developed by STM for use in space applications. Improvements in processor microarchitecture, bandwidth of the system-on-chip design, and operating frequency are expected to improve the computational capacity 10x – 16x compared to the GR740. In addition, the GR765 will provide significant reductions in power consumption compared to earlier generation SoCs.

Beyond this boost on processing performance, the memory bandwidth will also be significantly increased by the use of DDR2/3 SDRAM, the peripherals will be complemented by SerDes supporting among others the SpaceFibre standard, TTEthernet, TSN and several other enhancements.

Announcements of new products based on, and development tools for, the GR740 processor, as well as completely new products being released before the end of the year.